1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus such as a one- or two-dimensional photoelectric conversion apparatus for reading an image for a facsimile apparatus, an image scanner, a digital copying machine, or an X-ray image pickup apparatus and, more particularly, to removal of FPN (Fixed Pattern Noise).
2. Related Background Art
As an image read system for a facsimile apparatus, an image scanner, a digital copying machine, or an X-ray image pickup apparatus, a read system using a reduction optical system and a CCD has been used. However, recent development of a CIS (Contact Image Sensor) for a 1.times.-magnification system, in which a multiple of single-crystal silicon chips are mounted, is also remarkable.
FPN in such a multi-chip CIS in which a plurality of sensor chips are coupled is classified into FPN generated in a chip and FPN generated between chips. If the FPN is large, vertical stripes are generated on an image and adversely affect the image quality. Therefore, the FPN must be reduced to a minimum.
A technique of correcting FPN will be described with reference to FIGS. 7, 8, and 9. FIG. 7 is a circuit diagram of one bit of a one-dimensional photoelectric conversion apparatus having a photoelectric conversion device 9 for each pixel. FIGS. 8 and 9 are timing charts of the photoelectric conversion apparatus (Journal of the Society for Television, Vol. 47, No. 9 (1993), p. 1180).
The circuit operation and FPN removal will be described. Referring to FIG. 8, a start pulse SP is supplied to a shift register SR 39 in synchronism with a clock CLK to set a reset pulse .PHI.CR at "H" so as to turn on MOS transistors 15 and 16 and reset signal holding capacitors CTS 1 and CTN 2. The light amount of image is accumulated in the base of the photoelectric conversion device 9. When accumulation is complete, a transfer pulse .PHI.TS is set at "H" to turn on a transfer MOS transistor 13. A light signal containing noise is read out and transferred to the optical signal holding capacitor CTS 1. Next, a reset pulse .PHI.BRS is set at "H" to turn on a MOS transistor 11. A reset pulse .PHI.ERS is set at "H" to reset the sensor 9 of the photoelectric conversion device. After a predetermined time, a reset pulse .PHI.TN is set at "H" to turn on a noise transfer MOS transistor 14, so a noise component corresponding to a signal component in the photoelectric conversion device 9 which has no optical signal is transferred to the noise signal holding capacitor CTN 2. The reset pulse .PHI.BRS is set at "L", and the reset pulse .PHI.ERS is set at "H" to reset the sensor again, and the next accumulation is started. In this example, one read cycle of one photoelectric conversion device has been described. For photoelectric conversion devices of one line, the same circuit elements as in FIG. 7 which correspond to each photoelectric conversion device operate in a similar manner, so optical signal charges and noise signal charges of one line sensor are transferred to corresponding holding capacitors.
During accumulation, scanning is started in response to input pulses .PHI.1 and .PHI.2 which are phase-inverted by the shift register SR 39. First, a reset pulse .PHI.CHR is set at "H" to turn on reset MOS transistors 5 and 6, so an optical signal common output line 3 and a noise signal common output line 4 are reset. Thereafter, a scanning pulse from the shift register SR 39 is set at "H" to turn on scanning MOS transistors 17 and 18, so data in the signal holding capacitors CTS 1 and CTN 2 are divided by the capacitors of the common output lines and output to the common output lines 3 and 4, respectively. The common output lines have capacitors CHS 7 and CHN 8, respectively. The optical signal common output line will be defined as CHS 7, and the noise signal common output line as CHN 8 hereinafter. The signals output to the common output lines 3 and 4 are amplified by preamplifiers 19 and 20, respectively. The difference between the light signal component and the noise signal component is calculated by a differential amplifier 21. The difference signal is held by a clamp circuit 10, amplified by an amplifier 24, and output as an image signal. The reset pulse .PHI.CHR is set at "H" to turn on the reset MOS transistors 5 and 6, so the capacitors CHS 7 and CHN 8 of the common output lines are reset to a reference potential VCHR, and data of signal holding capacitors CTS and CTN for the next bit are read out.
FIG. 9 is a timing chart showing this read portion. The pulses .PHI.1 and .PHI.2 are input to the shift register SR 39, and the reset pulse .PHI.CHR for resetting the common output lines 3 and 4 is output in synchronism with the clock signal CLK. This operation is repeated at a period T to output signals of all bits. The output signal is input to the differential amplifier 21 through the preamplifiers 19 and 20 of voltage follower and output from the IC. FPN in the chip is generated mainly due to an hFE variation in the bipolar transistor 9 of each pixel. The hFE variation of each pixel can be canceled by the above S-N scheme which subtracts the noise signal component from the light signal component. As for FPN between chips, the sensor output is clamped to a reference potential VREF by the clamp circuit 10 shown in FIG. 6. The difference between chips corresponds to only the offset of the amplifier next to the clamp circuit 10 and can be reduced.
However, FPN cannot be sufficiently removed by the above techniques. In the prior art, it is assumed that the potentials of the common signal line capacitors CHS and CHN completely equal during a period A shown in FIG. 9, i.e., while the common signal line capacitors CHS and CHN are reset to the reference potential VCHR to float. In fact, after the common signal line capacitors CHS and CHN are reset, they have different potentials.
This may be attributed to the difference between the reset MOS transistors 5 and 6 for the common signal line capacitors CHS and CHN, or the difference between the common signal line capacitors CHS and CHN and the parasitic capacitance of a power supply line, a GND line, or various pulse lines.
The potential difference between the common signal line capacitors CHS and CHN, which is generated after the common signal line capacitors CHS and CHN are reset, results in disadvantages such as an increase in the FPN due to the level difference between odd-numbered bits and even-numbered bits of the photoelectric conversion device or the difference between chips. However, in an actual IC, this difference can hardly be completely removed, resulting in large difficulty in FPN reduction.